I decided not to use Interrupts in my design as Polling is much preferred in terms of bandwidth. This is an example of how Xilinx made an effort to ease the implementation phase with the XDMA for the average user. The addition of DMA_Reset_bridge feature is a life-saver for the cases where you did something wrong, and you want to reset everything except the link youвЂ™re using. It is simple to use and easy to implement in your designs. Other than that, Xilinx did a great job with this core. This may be sufficient for the average user, but when thinking ahead to a more sophisticated implementation of the DMA with this core, this is a show stopper. What it means, is if you do want to implement further enhancements (like adding more channels), this cannot be achieved, as all under the hood вЂ“ cannot be seen by the user. The XDMA is a Xilinx wrapper for the PCIe bridge. This means if you need more than 4 for your design, you cannot use this solution.Дў. There are only 4 RX DMA channels and only 4 TX DMA channels. Though they are not a deal-breaker from my point of view, still, the average user must know them before starting to work with this core:ДЎ. Xilinx XDMA, even if very easy to implement, and very straight forward, does have a few drawbacks. Taken from PCI Express Base Specification: It is a region of memory marked as prefetchable and the CPU can request in advance as an optimization. The Prefetchable option enables faster operations between the CPU and the memory. Now weвЂ™ve left with 2 last checkboxes: вЂ PrefetchableвЂ™ and вЂ64bit enableвЂ™. This seems logical if the BAR size is large enough, but in case there are multiple AXI peripherals that acquire access it could limit them and cause issues. Need to remember, though, that using the default value of 0 will cause all accesses to the BAR to be translated to a base address of 0 in AXI space. In other words, all accesses to the BAR will be translated to a base address of 0 in AXI space. No matter what address the host uses to place the PCIE BAR within the host address space, any host access to that BAR will translate to an AXI address of 0, in our case. The вЂ PCI to AXI TranslationвЂ™ translates the PCI address to AXI territory. For example, looking in my configuration below, you can see IвЂ™ve allocated 64MB of memory for the вЂPCI to AXI Lite Master InterfaceвЂ™ which means the register address space mapped could be the size of 64MB (so address space is ). Moving on to the next fields, these are the вЂ SizeвЂ™, вЂ ValueвЂ™ and вЂ PCI to AXI TranslationвЂ™ fields the вЂSizeвЂ™ and вЂValueвЂ™ fields are in charge of the allocated space used for this BAR.

Dma code table